The present disclosure relates to a history buffer that dynamically preserves targeted multiple-field registers.
Modern information handling systems typically implement out-of-order microprocessor designs that store register contents at “checkpoints” so the microprocessor can revert back to a register state prior to an interruption if required, such as during a branch instruction. When a processor reaches branch instruction, the processor selects a most likely path and begins to process instructions down the selected path. The processor, however, stores register contents at the branch in case the selected path is the incorrect path and the processor needs to revert back to the register state prior to the mis-predicted path.
Processors may store the register contents at checkpoints in history buffers. Traditional history buffers allow a processor to store the entire contents of a particular register in a history buffer entry, such as storing the entire contents of a general purpose register (GPR) into a single history buffer entry. Each history buffer entry includes a single instruction tag (itag) field that stores an itag value from the GPR, which the processor utilizes to determine which history buffer content should be restored into specific registers if required.
Unlike GPRs, however, exception and status registers consist of multiple fields that a processor may independently update (e.g., FPSCR, XER, CR, etc.). For example, an ADD instruction may update a register's CARRY and OVERFLOW fields without updating the register's FXCC (fixed-point condition code) field. Due to the fact that each register field may be written by a different instruction, each register field requires its own instruction tag (itag) to correspond with the instruction that updates the particular field.